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Ryzen AM5 Hynix 16Gb M-die DDR5 timings 2x16GB/2x32GB DDR5-6000 to DDR5-6400 V0.1 (Patreon)

Published:
2024-12-22 00:14:22
Edited:
2025-02-15 11:39:33
Imported:
2026-06

Downloads

Content

An expanded version of the original "easy Hynix timings". 16Gb M-die generally doesn't clock past 7000ish so all the settings here are for 1:1 mode since 2:1 mode at less tha 7600 doesn't perform well.

Comments

InkyBusiness

The constellation wr=48 wtrl<=wr/2 rddl>=wtrl*2 rtp>=wtrl/2 rdrdscl=rrdl-rrds+1 allows DDR5 to execute two writes per read. This is configuration yields a lower latency than forcing timings a bit lower. Lower timings pay of when much tighter. Timings allowing for this are for example: RRDS 8 RRDL 12 WTRS 4 WTRL 24 RDRDSCL = 12-8+1 = 5 Generally we have convinient numbers of especially ras that are higher than the the buildzoid timings, but will likely perform better, such as ras 36 being a multiple of rtp and burst or at least burst/2: Lots of little tweaks can be applied according to the architecture of DDR5

InkyBusiness
>>159028734

I expect better performance for most of the presented preset with slightly higher timings, that allow execute within two writes per read

Exostenza

I assume you made a mistake setting tRCDWR as 16 in the BZ lazy settings? Is it supposed to be 36?

InkyBusiness

A little sidenode on the command buffer configuration aka Nitro. Mobos default to rx 2, tx 3, cl 1. Lowering the read buffer ticks to 1, or disabled, improves latency drastically. Increasing it to 1 or 2 may theoretically yield a better rcdrd. I have not practically seen this have a postive effect on rcdrd. Lowering it below cl is useless though. . Leaving tx at 3 as it doesn't really have any adverse effect on latency or bandwidth, and lower values may worsen stability significantly. tx 3 may also enable wrrd 1 on systems that don't like it initially. All my DDR5 did do wrrd 1. Especially combining this with the two writes per read tweak does improve performance by a bit. . To the best of my knowledge, cl 1 is infact additive in latency to gear down mode, cl2 is gdm 1/4. 0 is gdm off. It should be the timings of the internal link between the umc and phy. But please do correct me here if I am incorrect.

buildzoid
>>159042531

For WRITE operations you don't need the ACT to completely fully. So you can have very very low tRCDWR

InkyBusiness
>>159028734

I have not isolated this in timespy extreme CPU. In Aida the difference in write of around 400mbps. I have however tested the combination of this tweak, wrrd 1, nitro tx 3 vs the best oc I had prior to this. We're looking at 4558 vs 4582 with a Ryzen 7500f at fixed 4.2GHz. . In any case your BZ lazy presents do fulfill this criteria. Just the fallback and "easy" does not. I am absolutely nitpicking here, there is no real world gain from any of those tweaks; they are just for the joy of pushing the oc. Rather I hope people who copy your timings do note that lowering some specific timings by just one tick may worsen performance. Especially when that timing ends up at a very odd fraction of a burst. . I could also note that the refi timing is best kept at 0xffff - 0x0fff * n - 1, such as 49154. Or ensuring that refi - rfc is a multiple of burst that is (refi + 1 - rfc + 1) % 8 = 0. But that has absolutely no measurable performance impact.

Vasily Morozko

Hi. I need some help, please. I am like super new to all of this. In this guide AHO have included tRCDWR and RD values separately but in my bios (ASUS b650e itx) I only have tRCD. Which tRCD value should I use then?

EumelEumel

tyvm 💖 How do you change tRCDWR on Asus MB? they seem to be tied together?

NotePad X

Tried these timing on my Asus B650E-E / 7800X3D / 2x32GB GSKILL Trident Z CL30 Hynix M dies. I think I must have done something wrong. Shouldnt i be getting better performance with this? https://imgur.com/a/6kbt0wx

Wongfamily

Unfortunately I purchased this today, but for me and my 9800x3d, Asus x670e-i with Tforce 6000 30-36-36-76 1.35v M-die sticks, the 6000mhz pages fallback and easy columns either don't get into windows or aren't stable :( I used the original ez timings with same setup for a very long time?

buildzoid
>>164545171

Did you try not copying the Primaries? Because the subtimings are pretty much the same as the old ez timings

Raul

Unable to open the attachment :(

Mike

Is there any downside to going above the FCLK’s listed? I found I can get to 2200mhz fclk on my 9800x3d without issue. I don’t see any where that fclk needs to be ratio’d with other speeds for these later zen chips. Or is there some kind of obvious detriment?

buildzoid
>>165710677

in 1:1 mode it's generally gonna be faster. For 2:1 the latency penalty for desyncing usually out wieghs the extra bandwidth

Mike
>>165710677

That’s great info. I am going to try some of your timings for my gskill 64gb kit. Timings have always been a pain for me, so these quick solutions are an awesome resource. I’m very impressed with the 9800x3d so far. I can run 1.26v and hold 5.5ghz all core, no de lid, just a basic thermalright water to air. I don’t run the typical gambit of stability testing, instead run my cad workloads +/- the games I might play, and or web pages I might open. So having a decent ram timing guide to work from or just use, has been the final overclocking resource I have always needed.

buildzoid
>>165710677

for 6000 and 6200 always for 6400 it might depend a bit on the workload(because 2133 is already really close to 2200 in bandwidth).

Mr.WhatZitTooya69

What die is CMH64GX5M2B6400C32 corsair Vengeance, I know it is hynix but a or m

Kyle Robertson
>>170838291

You have to look at the sticker on the RAM stick itself. 5.43.1 is A-die. 5.43.13 is M-die

Brian Wagner

For anyone who ran into this issue: My RAM was running perfectly stable with EXPO (t-create CTCED532G6000HC30DC01) 6000@30-36-36-76, but would error out on TM5 Absolut even on the "easy" and even the "fallback" settings, which surprised me. After a lot of trial and error setting tRTP from 16 to 17 did the trick, and I can now run the Buildzoid "Fallback" settings. The "Easy" settings, or even just trying to get timings to 32-37-37-126 with DRAM VDD @1.43, will still error out within a few minutes of TM5 Absolut. It could be an unlucky ram kit, but I've also read sometimes ITX boards are more susceptible to this. FWIW I have an AsRock B650i Lightning and a 9600X.

Brian Wagner
>>174757226

But thanks Buildzoid, absolutely would not have been able to figure this out on my own, and it's a noticeable and measurable performance difference over the EXPO settings.

KeinNiemand

Why is tRTP 16 here when it was 12 on the old easy timings, is 12 sometimes not stable on m die?

Jon

Hi. What value do you recommend to set for "Scalar" and "PBO Limits" parameters in Precision Boost Overdrive for AMD processors? I prefer "Motherboard" and "1X". Is it worth to set something else? (Games)

8vasa8

Hey, is this for ryzen 7000? Shoud I use v0.1 or v0.2. Thanks

Riotvan

I got the 6000 BZ lazy settings working except for the max trefi setting of 65k, the hottest module reaches 47.7C at which point it errors. But i don't trust the the ram fully seems to me that should still be an ok temp? There is a fan on it but since i run an air cooler it's a bit more tricky to get proper airflow, one of the sticks is covered by the cooler. I used the V02 guide.

buildzoid
>>187895264

that's kinda weird to be getting errors at a temp that low. Maybe give it a tad more VDD

Jordan Monsalve

Hey BZ, I’ve gotten 6200 (BZ Lazy) to run stable at 2200fclk. I am unable to get 1:1 6400. Question, will adding in the timing from the 6400 section benefit my 6200 1:1 BZ lazy or do I leave as is?

Np

what should i set vddq and vddio to? on my asrock mainboard there is no auto option and the default value is just 1.1

L4Jd

Hi BZ. I'm on a 9800X3D, 6200MT/s and 2067 FCKLK is stable with JEDEC timings. But as soon as i try to tighten the timings it throws errors after 5min in karhu (applied your table settings and already loosend tRCDRD & tRP) CL28, CL30, CL32 all are unstable. Vsoc@1.30 , Vdd@1.43. Is it my IMC or the Kingston 6000-CL30 kit? Any advice? ;)

Janosch Hoffmann

Hi, are there equivalent A-die pdfs posted. I can't seem to find them. Thanks!

Kim

Asura YT

Thanks a lot for the sheet. I've been watching your youtube videos where you disseminate knowledge on DDR5 tuning. I'm so sorry for your loss.

Hank

Are these timings still good?

Matías Bao

https://imgur.com/a/PO1GPVS sharing my progress so far, any advice is welcome. I'm trying to set tRCDWR to 16 but the value won't change despite typing 16 in the BIOS, any ideas of what it can be? Can't do tWTRS 2 and tWTRL 14. Tried 1.05 VSoC but fails in second iteration of LinPack VOLTAGES (BIOS) Infinity Fabric Frequency: 2200 MHz UCLK DIV1 Mode: UCLK = MEMCLK VDDIO Voltage (VDDIO_MEM_S3): 1.350 V DRAM VDD Voltage: 1.350 V DRAM VDDQ Voltage: 1.350 V DRAM VPP Voltage: 1.800 V SoC/Uncore OC Mode: Enabled SoC Voltage (VDDCR_SOC): Fixed Mode Fixed Voltage: 1.100 V VDDCR_SOC Load-Line Calibration: Level 3 VDDP Voltage: 0.950 V VDD Misc Voltage: 1.000 V VDDG CCD Voltage: 0.900 V VDDG IOD Voltage: 0.950 V