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DRAM timing examples

idle to 6RDs tRRD+tFAW+tRDRD ideal timing ns,CK,CMD,BG,Bank,Row/Col,DQ,notes 0.00,0,ACT,BgA,A,R123,relevant timings,settings 0.56,1,tCL,14,READ to data on DQ 1.11,2,tRCD,14,ACT to READ/WRITE 1.67,3,tRP,14,PRE to idle time 2.22,4,ACT,BgB,A,R234,tRAS,28,ACT to PRE 2.78,5,CR,1,command rate 3.33,6,tRTP